1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same. More specifically, the present invention relates to highly-integrating technology for memory cells of a dynamic random access memory (DRAM).
2. Description of the Related Art
In recent years, the miniaturization and high-integration of semiconductor memory devices, especially those of DRAMs, are making remarkable progress. In accordance with this, more and more memory cells with very limited areas have been developed.
In the past, DRAMs have been miniaturized and integrated, without changing the planar structure of the cell transistors of memory cells. For this reason, the cell transistors have become very hard to design. To be more specific, planar type cell transistors must suppress a short channel effect and have an improved retention characteristic, but these two requirements are hard to satisfy simultaneously when they are miniaturized. In effect, further improvement cannot be expected on this matter. Nevertheless, there is a requirement that the cell areas be reduced further.
FIGS. 16A and 16B show the cell structure of a conventional DRAM. FIG. 16A is a plan view showing the cell layout of an 8F2 type, for example, and FIG. 16B is a sectional view taken along line 16Bxe2x80x9416B of FIG. 16A.
As shown in these Figures, the occupation area of one memory cell is determined by planar type cell transistor 101, one bit line contact (CB) 103 shaped by two cells, and an element isolation region 105. In FIGS. 16A and 16B, reference numeral 107 denotes an active area (AA), numeral 109 denotes a p-type silicon substrate, numeral 111 denotes a word line, numeral 113 denotes an SiN film, numeral 115 denotes an interlayer film, numeral 117 denotes a capacitor contact (storage node contact [CN]), and numeral 119 denotes a bit line (BL). Reference numeral 121 denotes a cell capacitor including a storage electrode (SN) 121a, a capacitor dielectric film 121b and a plate electrode (PL) 121c. 
Let us assume that a minimum working dimension is F and that a gate electrode (word line (WL)) 101a and a diffusion layer 101b (which is to function as a source or drain) have sides that are designed based on F. In this case, the minimum occupation area of a memory cell is 8F2 (the length is 2F, and the width is 4F). As can be seen from this, the miniaturization and integration of a DRAM wherein each memory cell includes one transistor and one capacitor have made progress based on the 8F2 type cell layout.
In the planar type cell transistor 101, however, the gate length decreases in accordance with a decrease in the cell area, and the short channel effect is hard therefore to suppress. To effectively suppress the short channel effect, a leak between depletion layers 101b should be reduced, and this is attained by increasing the boron concentration of a channel section (in the case where a substrate 109 is a p-type). On the other hands, it is required that the retention characteristic be further improved since the retention characteristic plays an important role in determining the performance of a DRAM. To improve the retention characteristic, the junction leak at the capacitor side, which adversely affects the retention characteristic, must be reduced. This is attained by decreasing the boron concentration of the channel section in the neighborhood of the capacitor-side junction (in the case where the substrate is a p-type).
As described above, in the DRAM, one requirement is attained by increasing the impurity concentration in the channel section of a cell, and another requirement is attained by decreasing the same impurity concentration. In other words, these requirements are in trade-off relationships in terms of the impurity concentration of the channel section. Moreover, the recent severe cost competition requires that the cell area be further reduced and the chips (DRAM) be further miniaturized and integrated. However, in the 8F2 type cell layout shown in FIG. 16A, the cell area is already that of the theoretical limitation (i.e., the cell area is none other than 8F2). Under the circumstances, the required reduction in the cell areas cannot be attained, and the further miniaturization and integration of chips cannot be met.
As described above, further reduction in the size of cell areas and further miniaturization and integration of chips are required in the conventional art. These requirements, however, cannot be met since the suppression of the short channel effect of a cell transistor and the improvement of the retention characteristic are hard to satisfy simultaneously in the case of the 8F2 type cell layout.
A semiconductor memory device according to an embodiment of the present invention comprises: a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate, the columnar portions being isolated by a plurality of trenches having first and second bottoms which are different in depth; a plurality of cell transistors including first diffusion layer regions formed in the first bottoms shallower than the second bottoms, second diffusion layer regions formed in surface portions of the columnar portions, and a plurality of gate electrodes which are adjacent to the first and second diffusion layer regions and extending along one side surface of each columnar portion; a plurality of word lines connected to the gate electrodes, respectively; a plurality of bit lines extending in a direction intersecting with the word lines and connected to the first diffusion layer regions, respectively; and a plurality of cell capacitors connected to the second diffusion layer regions, respectively.
A semiconductor memory device-manufacturing method according to an embodiment of the present invention comprises: providing a plurality of columnar portions by forming a plurality of first trenches of a first depth in memory cell array regions of a semiconductor substrate; forming a plurality of first diffusion layer regions by forming first impurity layers in bottoms of the first trenches; filling the first trenches with a gate electrode material; selectively removing the gate electrode material from the first trenches by forming a plurality of second trenches of a second depth deeper than the first depth, such that a plurality of gate electrodes extend at least along one-side portions of the columnar portions; forming a plurality of element isolation regions by filling the second trenches with an insulating film; forming a plurality of word lines which are connected to the gate electrodes; forming a plurality of second diffusion layer regions by forming second impurity layers in surface portions of the columnar portions; forming a plurality of bit line contacts which are connected to the first diffusion layer regions; forming a plurality of bit lines which are connected to the bit line contacts; forming a plurality of capacitor contacts which are connected to the second diffusion layer regions; and forming a plurality of cell capacitors which are connected to the capacitor contacts.